Typically, integrated circuit devices can have interface pads that provide external connections to circuit structures, and include some sort of protection against ESD events. An ESD event can include the transfer of a significant amount of electrical energy to an integrated circuit interface pad in a very short time (usually tens to hundreds of nanoseconds). The integrated circuit must be capable of dissipating the energy from the ESD event to prevent damage to circuits contained in the integrated circuit.
To assist in understanding various of the disclosed embodiments, a conventional ESD protection circuit will first be described.
Referring now to FIG. 6, a conventional ESD protection circuit is shown in a schematic diagram and designated by the general reference character 600. An ESD protection circuit 600 can include an input pad 602, an input resistance 604, an input buffer circuit 606, a local clamp 608, and an input ESD protection structure 610. Local clamp 608 and input buffer circuit 606 can be connected to a low power supply connection (VSS). Circuit 600 can also include an ESD protection structure 610 connected to input pad 602. A power supply connection VSS can include an inherent resistance Rs, due to conductive lines, diffusions, contact resistance, etc.
An ESD event at input pad 602 can result in a potential building with respect to a low power supply line and input pad 602, particularly if a resistance VSS is not insubstantial (e.g., greater than 1 ohm). Local clamp 608 can be an n-channel metal-oxide-semiconductor (MOS) device in a grounded-gate configuration. Thus, local clamp 608 can protect gates of the transistors within input buffer circuit 606 by clamping such gates to a VSS node 612 once a potential exceeds a threshold voltage of the transistor.
Although not shown in FIG. 6, an ESD protection arrangement can also include a clamping device between power supply voltage nodes that can clamp such supply nodes together during an ESD event.
ESD events can take a variety of forms. Four particular types will now be described with reference to FIG. 6. A first type of ESD event can be a negative “zap” at input pad 602 with respect to a low power supply node. In such an arrangement, a p-n junction within ESD protection structure 610, formed by a p-type substrate and n+ source, can forward bias, clamping input pad 602 to VSS node 612.
A second type of ESD event can be a negative zap at input pad 612 with respect to a high power supply node. Initially, the above described p-n junction of ESD protection structure 610 can forward bias, causing low power supply node 612 to drop in potential, while a high power supply node remains at a ground potential. Eventually, a main clamping device between a high power supply node and low power supply node will “snap back” due to an excessive drain-to-source (Vds) potential. It is understood that clamp-type ESD protection devices can be designed with special layout instructions, and thus can recover from such events.
A third type of ESD event can be a positive zap at input pad 602 with respect to a low power supply voltage node. In such an event, an excessive Vds can build across ESD protection device 610, and the device can snap back.
A fourth type of ESD event can be a positive zap at input pad 602 with respect to a high power supply voltage node. In this case, ESD protection device 610 can snap back, pulling up the potential at a low power supply node 612. In the case where device 610 has a body region formed in a p-type substrate, the entire integrated device can function as a large diode, with n-type wells (which have bias connections to a high power supply node via n+ type tap diffusions) forming diodes with the p-type substrate (which have bias connections to a low power supply node via p+ type tap diffusions). In the event input pad 602 has a low supply connection that is not a p-type substrate, the integrated circuit device can include back-to-back diodes that connect such a node to the substrate. Such back-to-back diodes will eventually conduct in an ESD event, providing the same type clamping effect.
A drawback to a conventional approach like that of FIG. 6 can be the constraints introduced into device design by having to include a local clamp. In particular, a local clamp is typically provided in close proximity to each input buffer, and thus can make input buffer design awkward. This can be further complicated by special layout rules that may be required for n-channel devices included in ESD protection circuits. Still further, a local clamp can typically be a relatively large device, and thus can be difficult to accommodate in dense layout areas and/or can compromise critical layout areas (those requiring matching). Finally, in a normal mode of operation, the grounded-gate of NMOS device of local clamp 608 can present an additional capacitive load at the input.